3. (25 Pts) Design A Circuit That Converts Any 3-bit Number To Its Negative In Two's Complement System

3. (25 Pts) Design A Circuit That Converts Any 3-bit Number To Its Negative In Two's Complement System

Introduction

In digital systems and computer architecture, representing signed numbers efficiently is crucial for performing arithmetic operations such as addition, subtraction, and multiplication. The two's complement system is the most widely used method for representing signed integers in binary form because it simplifies the hardware design for arithmetic operations.

Designing a circuit capable of converting any 3-bit number into its negative in two's complement is a fundamental task in digital electronics. Such a circuit is not only essential for understanding number representations but also serves as a building block for more complex arithmetic logic units (ALUs) in microprocessors. Whether you are a student learning digital design or an engineer developing embedded systems, understanding how to implement this conversion efficiently is vital.

This article explores the detailed process of designing a 3-bit two's complement converter circuit. We will delve into the principles behind two's complement representation, step-by-step logic for the conversion, and the practical implementation of the circuit using basic logic gates. By the end of this guide, you will have a comprehensive understanding of how to design, analyze, and implement such a circuit.

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Understanding Two's Complement Representation

Before designing the circuit, it is essential to understand how two's complement encoding works for 3-bit numbers.

What is Two's Complement?

Two's complement is a binary number system that allows for straightforward binary addition and subtraction of signed integers. It encodes both positive and negative numbers in a fixed number of bits.

Representing Numbers in 3 bits:

| Decimal | Binary (unsigned) | Binary (2's complement) | Explanation |
|---------|---------------------|-------------------------|----------------------------------------------|
| 0 | 000 | 000 | Zero |
| 1 | 001 | 001 | Positive one |
| 2 | 010 | 010 | Positive two |
| 3 | 011 | 011 | Positive three |
| -1 | 111 | 111 | Negative one (two's complement) |
| -2 | 110 | 110 | Negative two |
| -3 | 101 | 101 | Negative three |

How to Find the Two's Complement:

To find the negative of a number:

1. Take the binary representation of the number.


2. Invert all bits (1's complement).


3. Add 1 to the inverted bits.

For example, to find -3 in 3-bit:

• 3 in binary: 011


• Invert bits: 100


• Add 1: 100 + 001 = 101

Thus, 101 represents -3 in 3-bit two's complement.

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Objectives of the Circuit Design

The primary goal is to design a digital circuit that:

• Accepts a 3-bit binary number as input.


• Outputs the 3-bit binary equivalent of its negative in two's complement.

Key Steps in the Design Process

1. Input Representation: 3-bit input, labeled as A2, A1, A0 (most significant bit to least significant).


2. Conversion Logic: Implement the two's complement conversion, which involves:

• Bitwise inversion (complement)


• Addition of 1

3. Output Representation: 3-bit output, labeled as Y2, Y1, Y0.

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Logical Analysis of Two's Complement Conversion

To convert an input number \(A = A2A1A_0\) to its negative:

\[
\text{Negative} = \text{Two's complement of } A = \overline{A} + 1
\]

Where:

• \(\overline{A}\) is the bitwise complement of A.


• The '+1' is added to the complemented bits.

Step 1: Bitwise Inversion

The first step is to invert all bits:

\[
\overline{A2} = \text{NOT } A2
\]
\[
\overline{A1} = \text{NOT } A1
\]
\[
\overline{A0} = \text{NOT } A0
\]

Step 2: Add 1 to the Inverted Bits

Adding 1 to the inverted bits involves a binary addition operation, which can be implemented using full adders.

The sum:

\[
Y = \overline{A} + 1
\]

can be broken down as:

\[
Y0 = \overline{A0} + 1
\]
\[
Y1 = \overline{A1} + \text{carry from previous addition}
\]
\[
Y2 = \overline{A2} + \text{carry from previous addition}
\]

This process can be simplified in hardware using XOR and AND gates.

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Designing the Circuit

The circuit consists of two main parts:

1. Bitwise inversion of input bits


2. Adding 1 (binary incrementation)

Part 1: Inversion Logic

• Use three NOT gates, each inverting one input bit.


• Outputs: \(\overline{A2}\), \(\overline{A1}\), \(\overline{A_0}\).

Part 2: Addition of 1

• Implemented using full adders for each bit.


• The least significant bit (LSB) addition involves adding \(\overline{A_0}\) and 1.


• Carry outputs from each adder are fed into the next adder for higher bits.

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Full Circuit Diagram Concept

The complete circuit can be visualized as:

• Three NOT gates for inversion.


• Three full adders (or a combination of XOR, AND, OR gates) for addition.


• The initial carry-in for the least significant bit's adder is logic '1' to perform +1 addition.

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Step-by-Step Implementation

1. Inversion Stage:

• Inputs: A2, A1, A0


• Outputs: \(\overline{A2}\), \(\overline{A1}\), \(\overline{A_0}\)

1. Addition Stage:

• For \(Y0\): Add \(\overline{A0}\) and 1 (carry-in = 1)


• For \(Y1\): Add \(\overline{A1}\) and the carry from previous addition


• For \(Y2\): Add \(\overline{A2}\) and the carry from previous addition

1. Output:

• \(Y2, Y1, Y_0\) representing the negative number in two's complement.

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Practical Implementation Using Logic Gates

Components Needed:

• 3 NOT gates


• 3 XOR gates (for sum calculation)


• 3 AND gates (for carry calculation)


• 1 OR gate (for carry propagation)


• Additional logic to generate the initial carry-in (which is logic 1)

Implementation Steps:

1. Generate inverted bits:

• \(\overline{A2} = \text{NOT } A2\)


• \(\overline{A1} = \text{NOT } A1\)


• \(\overline{A0} = \text{NOT } A0\)

1. Add 1 to \(\overline{A_0}\):

• Sum: \(Y0 = \overline{A0} \oplus 1\)


• Carry out: \(C0 = \overline{A0} \& 1\)

1. Add \(\overline{A1}\) and carry \(C0\):

• Sum: \(Y1 = \overline{A1} \oplus C_0\)


• Carry out: \(C1 = \overline{A1} \& C_0\)

1. Add \(\overline{A2}\) and carry \(C1\):

• Sum: \(Y2 = \overline{A2} \oplus C_1\)


• Carry out can be ignored for 3-bit representation, as it indicates overflow.

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Simplified Boolean Expressions

The final output bits are:

\[
Y0 = \overline{A0} \oplus 1
\]
\[
Y1 = \overline{A1} \oplus C_0
\]
\[
Y2 = \overline{A2} \oplus C_1
\]

Where:

\[
C0 = \overline{A0} \& 1 = \overline{A_0}
\]
\[
C1 = \overline{A1} \& C_0
\]

Since adding 1 is equivalent to XOR with 1 for the least significant bit, the circuit simplifies to:

\[
Y0 = \overline{A0} \oplus 1 = \text{NOT } \overline{A0} = A0
\]

Similarly, the rest can be